High speed static random access memory (SRAM) architectures typically use a sense amplifier and two global read lines to load data into an output latch in a global input output (GIO) Block. This requires two operations finished before the sense amplifier starts discharging one of the global read lines. The first operation is a precharging of the global read lines should get completed before a sense amplifier enable signal arrives. The second operation is the global read lines precharging operation should is finished to avoid contention on the global read lines before the sense amplifier starts discharging one of the global read lines. Across various pressure, voltage and temperatures (PVTs) and instance sizes, it is difficult to meet the above two margin conditions and failure to meet these margins results in functional failure of the SRAMs and huge dynamic power consumption.